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<title>CMSIS-Core (Cortex-A): GICDistributor_Type Struct Reference</title>
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   <div id="projectname">CMSIS-Core (Cortex-A)
   &#160;<span id="projectnumber">Version 1.1.4</span>
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   <div id="projectbrief">CMSIS-Core support for Cortex-A processor-based devices</div>
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<div class="header">
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<a href="#pub-attribs">Data Fields</a>  </div>
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<div class="title">GICDistributor_Type Struct Reference<div class="ingroups"><a class="el" href="group__GIC__functions.html">Generic Interrupt Controller Functions</a></div></div>  </div>
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<p>Structure type to access the Generic Interrupt Controller Distributor (GICD)  
</p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a6ca67d9838ab3425864207c3a0399bd7"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a6ca67d9838ab3425864207c3a0399bd7">CTLR</a></td></tr>
<tr class="memdesc:a6ca67d9838ab3425864207c3a0399bd7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x000 (R/W) Distributor Control Register.  <a href="#a6ca67d9838ab3425864207c3a0399bd7">More...</a><br/></td></tr>
<tr class="separator:a6ca67d9838ab3425864207c3a0399bd7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a405823d97dc90dd9d397a3980e2cd207"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a405823d97dc90dd9d397a3980e2cd207">TYPER</a></td></tr>
<tr class="memdesc:a405823d97dc90dd9d397a3980e2cd207"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x004 (R/ ) Interrupt Controller Type Register.  <a href="#a405823d97dc90dd9d397a3980e2cd207">More...</a><br/></td></tr>
<tr class="separator:a405823d97dc90dd9d397a3980e2cd207"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acebf65dae4cb82cd3c7deeefca9c9722"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#acebf65dae4cb82cd3c7deeefca9c9722">IIDR</a></td></tr>
<tr class="memdesc:acebf65dae4cb82cd3c7deeefca9c9722"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x008 (R/ ) Distributor Implementer Identification Register.  <a href="#acebf65dae4cb82cd3c7deeefca9c9722">More...</a><br/></td></tr>
<tr class="separator:acebf65dae4cb82cd3c7deeefca9c9722"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae24f260e27065660a2059803293084f2"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#ae24f260e27065660a2059803293084f2">STATUSR</a></td></tr>
<tr class="memdesc:ae24f260e27065660a2059803293084f2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x010 (R/W) Error Reporting Status Register, optional.  <a href="#ae24f260e27065660a2059803293084f2">More...</a><br/></td></tr>
<tr class="separator:ae24f260e27065660a2059803293084f2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afbdd372578e2cd6f998320282cc8ed25"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#afbdd372578e2cd6f998320282cc8ed25">SETSPI_NSR</a></td></tr>
<tr class="memdesc:afbdd372578e2cd6f998320282cc8ed25"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x040 ( /W) Set SPI Register.  <a href="#afbdd372578e2cd6f998320282cc8ed25">More...</a><br/></td></tr>
<tr class="separator:afbdd372578e2cd6f998320282cc8ed25"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2f584d3fbeaa355faf234f2ee57d1168"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a2f584d3fbeaa355faf234f2ee57d1168">CLRSPI_NSR</a></td></tr>
<tr class="memdesc:a2f584d3fbeaa355faf234f2ee57d1168"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x048 ( /W) Clear SPI Register.  <a href="#a2f584d3fbeaa355faf234f2ee57d1168">More...</a><br/></td></tr>
<tr class="separator:a2f584d3fbeaa355faf234f2ee57d1168"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad55a8644bc95caf8bf53e1407ec9ed0c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#ad55a8644bc95caf8bf53e1407ec9ed0c">SETSPI_SR</a></td></tr>
<tr class="memdesc:ad55a8644bc95caf8bf53e1407ec9ed0c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x050 ( /W) Set SPI, Secure Register.  <a href="#ad55a8644bc95caf8bf53e1407ec9ed0c">More...</a><br/></td></tr>
<tr class="separator:ad55a8644bc95caf8bf53e1407ec9ed0c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab487e4a8684b8a77357c6c20cf71dead"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#ab487e4a8684b8a77357c6c20cf71dead">CLRSPI_SR</a></td></tr>
<tr class="memdesc:ab487e4a8684b8a77357c6c20cf71dead"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x058 ( /W) Clear SPI, Secure Register.  <a href="#ab487e4a8684b8a77357c6c20cf71dead">More...</a><br/></td></tr>
<tr class="separator:ab487e4a8684b8a77357c6c20cf71dead"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6a9effdd633c6e75651d9f53caace306"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a6a9effdd633c6e75651d9f53caace306">IGROUPR</a> [32]</td></tr>
<tr class="memdesc:a6a9effdd633c6e75651d9f53caace306"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x080 (R/W) Interrupt Group Registers.  <a href="#a6a9effdd633c6e75651d9f53caace306">More...</a><br/></td></tr>
<tr class="separator:a6a9effdd633c6e75651d9f53caace306"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1da3a2066b64644a0bb8a3066075ba87"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a1da3a2066b64644a0bb8a3066075ba87">ISENABLER</a> [32]</td></tr>
<tr class="memdesc:a1da3a2066b64644a0bb8a3066075ba87"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x100 (R/W) Interrupt Set-Enable Registers.  <a href="#a1da3a2066b64644a0bb8a3066075ba87">More...</a><br/></td></tr>
<tr class="separator:a1da3a2066b64644a0bb8a3066075ba87"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a390fa9f2f460951b2c6094932d890807"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a390fa9f2f460951b2c6094932d890807">ICENABLER</a> [32]</td></tr>
<tr class="memdesc:a390fa9f2f460951b2c6094932d890807"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x180 (R/W) Interrupt Clear-Enable Registers.  <a href="#a390fa9f2f460951b2c6094932d890807">More...</a><br/></td></tr>
<tr class="separator:a390fa9f2f460951b2c6094932d890807"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1c15cd75ce30d8946792e2a1a19556a5"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a1c15cd75ce30d8946792e2a1a19556a5">ISPENDR</a> [32]</td></tr>
<tr class="memdesc:a1c15cd75ce30d8946792e2a1a19556a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x200 (R/W) Interrupt Set-Pending Registers.  <a href="#a1c15cd75ce30d8946792e2a1a19556a5">More...</a><br/></td></tr>
<tr class="separator:a1c15cd75ce30d8946792e2a1a19556a5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0155cb4637845258e4ee76cd93cca2a6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a0155cb4637845258e4ee76cd93cca2a6">ICPENDR</a> [32]</td></tr>
<tr class="memdesc:a0155cb4637845258e4ee76cd93cca2a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x280 (R/W) Interrupt Clear-Pending Registers.  <a href="#a0155cb4637845258e4ee76cd93cca2a6">More...</a><br/></td></tr>
<tr class="separator:a0155cb4637845258e4ee76cd93cca2a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5eb8e1ef5a88293e2759c41f6057ccc4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a5eb8e1ef5a88293e2759c41f6057ccc4">ISACTIVER</a> [32]</td></tr>
<tr class="memdesc:a5eb8e1ef5a88293e2759c41f6057ccc4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x300 (R/W) Interrupt Set-Active Registers.  <a href="#a5eb8e1ef5a88293e2759c41f6057ccc4">More...</a><br/></td></tr>
<tr class="separator:a5eb8e1ef5a88293e2759c41f6057ccc4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac0fd4c1ad19b5a332e403bb9966ba967"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#ac0fd4c1ad19b5a332e403bb9966ba967">ICACTIVER</a> [32]</td></tr>
<tr class="memdesc:ac0fd4c1ad19b5a332e403bb9966ba967"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x380 (R/W) Interrupt Clear-Active Registers.  <a href="#ac0fd4c1ad19b5a332e403bb9966ba967">More...</a><br/></td></tr>
<tr class="separator:ac0fd4c1ad19b5a332e403bb9966ba967"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a08fa902293567e85dc6398dab58afaa9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a08fa902293567e85dc6398dab58afaa9">IPRIORITYR</a> [255]</td></tr>
<tr class="memdesc:a08fa902293567e85dc6398dab58afaa9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x400 (R/W) Interrupt Priority Registers.  <a href="#a08fa902293567e85dc6398dab58afaa9">More...</a><br/></td></tr>
<tr class="separator:a08fa902293567e85dc6398dab58afaa9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6f1b07d48d3a9199f2effec8492f721c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a6f1b07d48d3a9199f2effec8492f721c">ITARGETSR</a> [255]</td></tr>
<tr class="memdesc:a6f1b07d48d3a9199f2effec8492f721c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x800 (R/W) Interrupt Targets Registers.  <a href="#a6f1b07d48d3a9199f2effec8492f721c">More...</a><br/></td></tr>
<tr class="separator:a6f1b07d48d3a9199f2effec8492f721c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9b306a630388c795d3cd32fc2e23a2b5"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#a9b306a630388c795d3cd32fc2e23a2b5">ICFGR</a> [64]</td></tr>
<tr class="memdesc:a9b306a630388c795d3cd32fc2e23a2b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0xC00 (R/W) Interrupt Configuration Registers.  <a href="#a9b306a630388c795d3cd32fc2e23a2b5">More...</a><br/></td></tr>
<tr class="separator:a9b306a630388c795d3cd32fc2e23a2b5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae9eeb19ca95d0b95828f1f98700b5689"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html#ae9eeb19ca95d0b95828f1f98700b5689">IGRPMODR</a> [32]</td></tr>
<tr class="memdesc:ae9eeb19ca95d0b95828f1f98700b5689"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0xD00 (R/W) Interrupt Group Modifier Registers.  <a href="#ae9eeb19ca95d0b95828f1f98700b5689">More...</a><br/></td></tr>
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<tr class="memdesc:a6ac65c4a5394926cc9518753a00d4da1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0xF00 ( /W) Software Generated Interrupt Register.  <a href="#a6ac65c4a5394926cc9518753a00d4da1">More...</a><br/></td></tr>
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<tr class="memdesc:ae40b4a50d9766c2bbf57441f68094f41"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0xF20 (R/W) SGI Set-Pending Registers.  <a href="#ae40b4a50d9766c2bbf57441f68094f41">More...</a><br/></td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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<p>Clear Non-secure SPI Pending Register</p>
<table class="doxtable">
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
<tr>
<td align="left">[31:10] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[9:0] </td><td align="left">INTID </td><td align="left">The interrupt number to clear pending state from. </td></tr>
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          <td class="memname"><a class="el" href="core__ca_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t GICDistributor_Type::CLRSPI_SR</td>
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<p>Clear Secure SPI Pending Register</p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
<tr>
<td align="left">[31:10] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[9:0] </td><td align="left">INTID </td><td align="left">The interrupt number to clear pending state from. </td></tr>
</table>

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<p>SGI Clear-Pending Registers Each register corresponds to one software generated interrupt (SGI).</p>
<p>Reading from this register reveals</p>
<ul>
<li>0 - interrupt is not pending</li>
<li>1 - interrupt is pending</li>
</ul>
<p>Writing to this register causes</p>
<ul>
<li>0 - no effect</li>
<li>1 - removes the pending state </li>
</ul>

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<p>Distributor Control Register</p>
<p>When access is Secure, in a system that supports two Security states:</p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
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<td align="left">[31] </td><td align="left">RWP </td><td align="left">Indicates whether a register write is in progress or not. </td></tr>
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<td align="left">[30:8] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[7] </td><td align="left">EINWF </td><td align="left">Enable 1 of N Wakeup Functionality, if available. </td></tr>
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<td align="left">[6] </td><td align="left">DS </td><td align="left">Disable Security. </td></tr>
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<td align="left">[5] </td><td align="left">ARE_NS </td><td align="left">Affinity Routing Enable, Non-secure state. </td></tr>
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<td align="left">[4] </td><td align="left">ARE_S </td><td align="left">Affinity Routing Enable, Secure state. </td></tr>
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<td align="left">[3] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[2] </td><td align="left">EnableGrp1S </td><td align="left">Enable Secure Group 1 interrupts. </td></tr>
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<td align="left">[1] </td><td align="left">EnableGrp1NS </td><td align="left">Enable Non-secure Group 1 interrupts. </td></tr>
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<td align="left">[0] </td><td align="left">EnableGrp0 </td><td align="left">Enable Group 0 interrupts. </td></tr>
</table>
<p>When access is Non-secure, in a system that supports two Security states:</p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
<tr>
<td align="left">[31] </td><td align="left">RWP </td><td align="left">Indicates whether a register write is in progress or not. </td></tr>
<tr>
<td align="left">[30:5] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[4] </td><td align="left">ARE_NS </td><td align="left">Affinity Routing Enable, Non-secure state. </td></tr>
<tr>
<td align="left">[3:2] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[1] </td><td align="left">EnableGrp1A </td><td align="left">Enable Non-secure Group 1 interrupts. </td></tr>
<tr>
<td align="left">[0] </td><td align="left">EnableGrp1 </td><td align="left">Enable Non-secure Group 1 interrupts. </td></tr>
</table>
<p>When in a system that supports only a single Security state:</p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
<tr>
<td align="left">[31] </td><td align="left">RWP </td><td align="left">Indicates whether a register write is in progress or not. </td></tr>
<tr>
<td align="left">[30:8] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[7] </td><td align="left">EINWF </td><td align="left">Enable 1 of N Wakeup Functionality, if available. </td></tr>
<tr>
<td align="left">[6] </td><td align="left">DS </td><td align="left">Disable Security. </td></tr>
<tr>
<td align="left">[5] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[4] </td><td align="left">ARE </td><td align="left">Affinity Routing Enable. </td></tr>
<tr>
<td align="left">[3:2] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[1] </td><td align="left">EnableGrp1 </td><td align="left">Enable Group 1 interrupts. </td></tr>
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<td align="left">[0] </td><td align="left">EnableGrp0 </td><td align="left">Enable Group 0 interrupts. </td></tr>
</table>

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<p>Interrupt Clear-Active Registers</p>
<p>Each bit corresponds to one interrupt:</p>
<ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>Bits corresponding to unimplemented interrupts are RAZ/WI. </dd></dl>

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<p>Interrupt Clear-Enable Registers</p>
<p>Each bit corresponds to one interrupt:</p>
<ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>Bits corresponding to unimplemented interrupts are RAZ/WI. </dd></dl>

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<p>Interrupt Configuration Registers</p>
<p>Each interrupt can be configured by two corresponding bits:</p>
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
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<td align="left">[2*INTID%16+1] </td><td align="left">Edge </td><td align="left">Interrupt is: 0 - level sensitive, 1 - edge triggered </td></tr>
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<td align="left">[2*INTID%16] </td><td align="left">Model </td><td align="left">0 - N-N Model, 1 - 1-N Model; RAZ/WI when unsupported </td></tr>
</table>

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<p>Interrupt Clear-Pending Registers</p>
<p>Each bit corresponds to one interrupt:</p>
<ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>Bits corresponding to unimplemented interrupts are RAZ/WI. </dd></dl>

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<p>Interrupt Group Registers</p>
<p>Each bit corresponds to one interrupt:</p>
<ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32</li>
</ul>
<p>And the value denotes:</p>
<ul>
<li>0 When <a class="el" href="structGICDistributor__Type.html#a6ca67d9838ab3425864207c3a0399bd7">CTLR</a>.DS==1, the corresponding interrupt is Group 0<br/>
 When <a class="el" href="structGICDistributor__Type.html#a6ca67d9838ab3425864207c3a0399bd7">CTLR</a>.DS==0, the corresponding interrupt is Secure.</li>
<li>1 When <a class="el" href="structGICDistributor__Type.html#a6ca67d9838ab3425864207c3a0399bd7">CTLR</a>.DS==1, the corresponding interrupt is Group 1.<br/>
 When <a class="el" href="structGICDistributor__Type.html#a6ca67d9838ab3425864207c3a0399bd7">CTLR</a>.DS==0, the corresponding interrupt is Non-secure Group 1. </li>
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<p>Interrupt Group Modifier Registers</p>
<p>Each bit corresponds to one interrupt:</p>
<ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32 </li>
</ul>

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<p>Distributor Implementer Identification Register</p>
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
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<td align="left">[31:24] </td><td align="left">ProductID </td><td align="left">An IMPLEMENTATION DEFINED product identifier </td></tr>
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<td align="left">[23:20] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[19:16] </td><td align="left">Variant </td><td align="left">An IMPLEMENTATION DEFINED variant number. </td></tr>
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<td align="left">[15:12] </td><td align="left">Revision </td><td align="left">An IMPLEMENTATION DEFINED revision number. </td></tr>
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<td align="left">[11:0] </td><td align="left">Implementer </td><td align="left">Contains the JEP106 code of the company implemented the GICD. </td></tr>
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<p>Interrupt Priority Registers</p>
<p>A GIC might implement fewer than eight priority bits, but must implement at least bits [7:4] of each field. In each field, unimplemented bits are RAZ/WI.</p>
<dl class="section note"><dt>Note</dt><dd>A register field corresponding to an unimplemented interrupt is RAZ/WI. </dd></dl>

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<p>Interrupt Routing Registers</p>
<table class="doxtable">
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
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<td align="left">[63:40] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[39:32] </td><td align="left">Aff3 </td><td align="left">Affinity level 3, the least significant affinity level field. </td></tr>
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<td align="left">[31] </td><td align="left">IRM </td><td align="left">Interrupt Routing Mode. Defines how SPIs are routed in an affinity hierarchy. </td></tr>
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<td align="left">[30:24] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[23:16] </td><td align="left">Aff2 </td><td align="left">Affinity level 2, an intermediate affinity level field. </td></tr>
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<td align="left">[15:8] </td><td align="left">Aff1 </td><td align="left">Affinity level 1, an intermediate affinity level field. </td></tr>
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<td align="left">[7:0] </td><td align="left">Aff0 </td><td align="left">Affinity level 0, the most significant affinity level field. </td></tr>
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<p>Interrupt Set-Active Registers</p>
<p>Each bit corresponds to one interrupt:</p>
<ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>Bits corresponding to unimplemented interrupts are RAZ/WI. </dd></dl>

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<p>Interrupt Set-Enable Registers</p>
<p>Each bit corresponds to one interrupt:</p>
<ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>Bits corresponding to unimplemented interrupts are RAZ/WI. </dd></dl>

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          <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICDistributor_Type::ISPENDR[32]</td>
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<p>Interrupt Set-Pending Registers</p>
<p>Each bit corresponds to one interrupt:</p>
<ul>
<li>Register index is given by INTID/32</li>
<li>Bit number is given by INTID%32</li>
</ul>
<dl class="section note"><dt>Note</dt><dd>Bits corresponding to unimplemented interrupts are RAZ/WI. </dd></dl>

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          <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint8_t GICDistributor_Type::ITARGETSR[1020]</td>
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<p>Interrupt Processor Targets Registers</p>
<p>Each bit in the target field corresponds to one CPU interface. A CPU targets field bit that corresponds to an unimplemented CPU interface is RAZ/WI.</p>
<table class="doxtable">
<tr>
<th align="left">CPU target field value </th><th align="left">Interrupt targets  </th></tr>
<tr>
<td align="left">0bxxxxxxx1 </td><td align="left">CPU interface 0 </td></tr>
<tr>
<td align="left">0bxxxxxx1x </td><td align="left">CPU interface 1 </td></tr>
<tr>
<td align="left">0bxxxxx1xx </td><td align="left">CPU interface 2 </td></tr>
<tr>
<td align="left">0bxxxx1xxx </td><td align="left">CPU interface 3 </td></tr>
<tr>
<td align="left">0bxxx1xxxx </td><td align="left">CPU interface 4 </td></tr>
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<td align="left">0bxx1xxxxx </td><td align="left">CPU interface 5 </td></tr>
<tr>
<td align="left">0bx1xxxxxx </td><td align="left">CPU interface 6 </td></tr>
<tr>
<td align="left">0b1xxxxxxx </td><td align="left">CPU interface 7 </td></tr>
</table>

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          <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICDistributor_Type::NSACR[64]</td>
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<p>Non-secure Access Control Registers</p>
<p>Each two bits corresponds to one interrupt:</p>
<ul>
<li>Register index is given by INTID/16</li>
<li>Bit number is given by 2*INTID%16</li>
</ul>
<p>The possible values of each 2-bit field are:</p>
<ul>
<li>00 - Non-secure accesses to all fields associated with the corresponding interrupt are permitted.</li>
<li>01 - Non-secure accesses are only permitted to requesting fields.</li>
<li>10 - As 01, additionally accesses to clearing field are permitted.</li>
<li>11 - As 10, additionally accesses to target and routing fields are permitted. </li>
</ul>

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<p>Set Non-secure SPI Pending Register</p>
<table class="doxtable">
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
<tr>
<td align="left">[31:10] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[9:0] </td><td align="left">INTID </td><td align="left">The interrupt number to set pending state for. </td></tr>
</table>

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          <td class="memname"><a class="el" href="core__ca_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t GICDistributor_Type::SETSPI_SR</td>
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<p>Set Secure SPI Pending Register</p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
<tr>
<td align="left">[31:10] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[9:0] </td><td align="left">INTID </td><td align="left">The interrupt number to set pending state for. </td></tr>
</table>

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          <td class="memname"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t GICDistributor_Type::SGIR</td>
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<p>Software Generated Interrupt Register</p>
<table class="doxtable">
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
<tr>
<td align="left">[31:26] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[25:24] </td><td align="left">TargetFilterList </td><td align="left">Determines how the Distributor processes the requested SGI. </td></tr>
<tr>
<td align="left">[23:16] </td><td align="left">CPUTargetList </td><td align="left">When TargetListFilter is 00, this field defines the CPU interfaces to which the Distributor must forward the interrupt. </td></tr>
<tr>
<td align="left">[15] </td><td align="left">NSATT </td><td align="left">Specifies the required group of the SGI. </td></tr>
<tr>
<td align="left">[14:4] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[3:0] </td><td align="left">INTID </td><td align="left">The INTID of the SGI to forward to the specified CPU interfaces. </td></tr>
</table>
<p>Refer to <a class="el" href="structGICDistributor__Type.html#a6f1b07d48d3a9199f2effec8492f721c">ITARGETSR</a> for details on TargetFilterList field. </p>

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<p>SGI Set-Pending Registers Each register corresponds to one software generated interrupt (SGI).</p>
<p>Reading from this register reveals</p>
<ul>
<li>0 - interrupt is not pending</li>
<li>1 - interrupt is pending</li>
</ul>
<p>Writing to this register causes</p>
<ul>
<li>0 - no effect</li>
<li>1 - adds the pending state </li>
</ul>

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          <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICDistributor_Type::STATUSR</td>
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<p>Error Reporting Status Register</p>
<table class="doxtable">
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
<tr>
<td align="left">[31:4] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[3] </td><td align="left">WROD </td><td align="left">Write to an RO location. </td></tr>
<tr>
<td align="left">[2] </td><td align="left">RWOD </td><td align="left">Read of a WO location. </td></tr>
<tr>
<td align="left">[1] </td><td align="left">WRD </td><td align="left">Write to a reserved location. </td></tr>
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<td align="left">[0] </td><td align="left">RRD </td><td align="left">Read of a reserved location. </td></tr>
</table>

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          <td class="memname"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t GICDistributor_Type::TYPER</td>
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<p>Interrupt Controller Type Register</p>
<table class="doxtable">
<tr>
<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
<tr>
<td align="left">[31:16] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
<tr>
<td align="left">[15:11] </td><td align="left">LSPI </td><td align="left">Maximum number of lockable shared interrupts. </td></tr>
<tr>
<td align="left">[10] </td><td align="left">SecurityExtn </td><td align="left">Security Extensions: 0 - not implemented. 1 - implemented. </td></tr>
<tr>
<td align="left">[9:8] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[7:5] </td><td align="left">CPUNumber </td><td align="left">Number of implemented CPU interfaces [=CPUNumber+1] </td></tr>
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<td align="left">[4:0] </td><td align="left">ITLinesNumber </td><td align="left">Maximum number of interrups supported [=32*(ITLinesNumber+1)]. </td></tr>
</table>

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